1. Field of the Invention
This invention relates generally to atomically flat surfaces, and, more specifically, to a method for forming atomically flat surfaces on a crystalline substrate or on a substrate with crystal texture.
2. Description of the Related Art
Today, the importance of technology based on advanced crystalline materials processing and the miniaturization of devices requires an unprecedented control on the composition and the structure of these materials and their surfaces/interfaces, in many cases down to the atomic level. Examples of these technologies are semiconductor fabrication/processing techniques and high density magnetic-recording devices.
But even the most perfectly polished crystalline materials (as used in actual devices) present surfaces far from flat at nanometer/atomic scales. They are populated with a high density of atomic steps when examined at the sub-micron scale. Even with the most precise cutting of metal or semiconductor slices from boules or ingots of these materials, perfect alignment of the cutting plane with the direction of atomic planes within the boules is not possible, resulting at the atomic level in a stepped profile across the face of the substrate. Yet with further miniaturization of devices, atomic steps under a feature can affect performance, creating the need for atomically flat surfaces.
Currently, when a flat region on the surface is required, one can search the sample to find regions of flatness or terraces. Sometimes, with luck, it is possible to find a naturally formed isolated flat region of small area. Other approaches in the silicon fabrication area have involved the patterning of areas across a wafer using focused ion beam milling (FIB) or standard lithographic techniques, followed by etching to form islands or trenches. Once the patterns are formed on the wafer through standard etching techniques, annealing techniques can be used to create the desired flat areas. As a result of the pre-patterning and annealing, atomic steps on the surface are re-arranged in such ways that step-density is very high in certain regions (for example at the edges of islands or trenches) while, simultaneously, step density is extremely low and can be zero in other regions (for example near the centers of islands or trenches). Such processes are described by S. Tanaka et al., Appl. Phys. Lett., 60, 1235 (1966), T. Ogino et al., Acc. Chem. Res., 32, 447 (1998), D. Lee et al., Surf. Sci., 445, 32-40 (1999), A. Cuenat et al., Adv. Materl, 17, 2845 (2005), and J. Lian et al., Nano Lett., 6, 1047 (2006). So far these processes have only been used on semiconductor wafers. Requiring lithographic steps, the effort and time/cost associated with these processes scales with the amount of surface are that is flattened. Particularly in the case of FIB processing, this is an important economic factor. Clearly, economic advantage would be anticipated in the case of processes that replace lithographic patterning with self-assembled patterns, as has been done in the invention described herein.